TPI Global Solutions

Compensation

Full Description

We are hiring a Performance Modeling / Verification Engineer (Intermediate) to support advanced system-level performance analysis and validation for next-generation hardware platforms. This role is focused on SystemC and Transaction-Level Modeling (TLM), working closely with architecture and verification teams to develop high-fidelity performance models used in system-level design decisions. The ideal candidate brings strong hands-on SystemC modeling experience, solid C++ programming skills, and practical exposure to performance validation and verification methodologies. Key Responsibilities • Develop, enhance, and maintain SystemC / TLM2 performance models for memory controllers, interconnects, and peripherals • Perform architecture exploration and performance analysis using cycle-approximate models • Identify system bottlenecks and optimize models to meet performance targets • Build and execute SystemC-based testbenches for functional and performance validation • Collaborate with cross-functional, globally distributed engineering teams • Integrate models into system-level tools and workflows • Create clear technical documentation covering model behavior, usage, and assumptions Required Qualifications • Minimum 5+ years of recent, hands-on SystemC experience • Strong understanding of Transaction-Level Modeling (TLM / TLM2.0) • Proficiency in C++ programming • Experience in performance modeling and system-level validation • Exposure to verification concepts, including simulation and debugging • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science Preferred Qualifications • Knowledge of memory controller architectures such as DDR or LPDDR • Familiarity with AXI / AHB bus architectures • Exposure to SV/UVM verification methodologies • Experience using Git or Perforce • Strong debugging skills in complex, multi-module environments Interview Process • One-hour technical interview with a senior engineer