$120K - 180K a year
Develop and maintain UVM-based verification environments, implement coverage models, debug verification issues, manage regressions, and collaborate with cross-functional teams.
7-15 years experience in front-end DV engineering with strong UVM verification skills, debugging expertise, and ability to mentor junior engineers.
We’re looking for 2-3 Front-end DV engineers with skills outlined below based in Canada. East coast would be preferred but we can look throughout. We need to find someone with 7-15 years experience. Key responsibilities: • Review and as needed develop comprehensive test plan strategies and ability to prioritize features based on architecture, specification, design knowledge, and feedback • Strong skills in creating and maintaining UVM-based verification environments, including writing testbenches, sequences and integrating reusable component architectures • Implement functional coverage models and ensure coverage closure for blocks and subsystems • Ability to debug complex design and verification issues using industry best practices and advanced tools • Assist with assertion-based verification, code coverage analysis, and regression management • Write and maintain verification scripts to streamline verification workflows and regression monitoring • Monitor regressions, triage failures, and drive resolution by collaborating with design and verification teams • Work closely with cross-functional teams, including architects, designers, software/firmware engineers, to ensure seamless integration and verification • Strong collaboration skills and initiative to reach out to FTE engineers on the verification of IP, subsystems, or SoCs during verification planning and debug of existing blocks and subsystems • Ability to mentor and guide junior engineers when needed
This job posting was last updated on 10/14/2025