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ME

Meta

via In-house

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ASIC Engineer, Design Verification

Anywhere
Full-time
Posted 1/6/2026
Direct Apply
Key Skills:
SystemVerilog
UVM
Verification IP
Constraint Random Testbench
Debugging design
Functional Coverage
Automation Scripting
Regression management

Compensation

Salary Range

$238K - 288K a year

Responsibilities

Define and implement IP/SoC verification plans, develop verification test benches, and collaborate with cross-functional teams to ensure design quality.

Requirements

Requires a Bachelor's degree and three years of experience in SystemVerilog/UVM, IP/SoC verification, debugging, functional coverage, automation scripting, regression management, and verification IP.

Full Description

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. To apply, click “Apply to Job” online on this web page. Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification and develop functional tests based on verification test plan. Collaborate with cross-functional teams like Design, Model, Emulation, and and Silicon validation teams towards ensuring the highest design quality. Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies from the industry. Telecommuting from anywhere in the U.S. allowed. Minimum Qualifications Requires a Bachelor’s degree (or foreign degree equivalent) in Computer Science, Electronics Engineering, or related field or a related field and three years of work experience in the job offered or in an engineering relatedoccupation Requires three years of experience in the following System Verilog / UVM Constraint Random Testbench IP/SoC (System On Chip) Verification Debugging design Functional Coverage Automation Scripting Regression management and Verification IP $238,228/year to $287,650/year + bonus + equity + benefits

This job posting was last updated on 1/7/2026

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