Eximietas Design

Perform RTL and gate-level power analysis and optimization, drive power-efficient design strategies, and mentor engineers. | Over 10 years of experience in power analysis and optimization, with expertise in RTL and gate-level analysis, and scripting skills in TCL, Python, or Perl. | Eximietas Design Hiring | Power Engineers & Power Leads Location: San Francisco Bay Area, CA (US) Experience: 5- 10+ years Availability: Immediate / Short notice preferred Eximietas Design is expanding its semiconductor design team in the US and is looking for experienced Power Engineers and Power Leads to work on cutting-edge SoC designs. If power analysis and optimization is your strength, we’d love to connect. What You’ll Do • Perform RTL and gate-level power analysis and optimization • Drive power-efficient design strategies across the design flow • Analyze and reduce dynamic and leakage power • Work closely with RTL, Physical Design, and Verification teams • Support power signoff, debug, and ECO closure • Mentor and guide engineers (for Lead roles) What We’re Looking For • 10+ years of hands-on experience in Power Analysis & Optimization • Strong expertise in RTL and gate-level power analysis • Experience with one or more of the following tools: • PrimePower / PrimePower-RTL • PowerArtist • Strong scripting skills in TCL, Python, and/or Perl • Experience with advanced technology nodes is a plus Why Eximietas Design • Work on high-impact semiconductor projects • Collaborate with global design teams • Opportunity for technical leadership and growth • Engineering-driven, flexible culture Interested or know someone who might be a fit? You can apply, refer, or start a conversation by reaching out directly at mohini.tyagi@eximietas.design