Microsoft

Compensation

Full Description

Research Interns put inquiry and theory into practice. Alongside fellow doctoral candidates and some of the world's best researchers, Research Interns learn, collaborate, and network for life. Research Interns not only advance their own careers, but they also contribute to exciting research and development strides. During the 12-week internship, Research Interns are paired with mentors and expected to collaborate with other Research Interns and researchers, present findings, and contribute to the vibrant life of the community. Research internships are available in all areas of research, and are offered year-round, though they typically begin in the summer. Implement hardware emulation logic on FPGA platforms to model compute and memory subsystems. Develop Register Transfer Level (RTL) modules and integrate them into existing FPGA frameworks. Validate functional correctness and timing fidelity against architecture specifications. Collaborate with hardware and software teams to ensure alignment with system-level performance goals. Document design methodology, test results, and optimization strategies. Currently enrolled in a PhD program in Computer Science or a related STEM field. In addition to the qualifications below, you'll need to submit a minimum of two reference letters for this position as well as a cover letter and any relevant work or research samples. After you submit your application, a request for letters may be sent to your list of references on your behalf. Note that reference letters cannot be requested until after you have submitted your application, and furthermore, that they might not be automatically requested for all candidates. You may wish to alert your letter writers in advance, so they will be ready to submit your letter. Proficient understanding of digital design principles and hardware description languages (Verilog/SystemVerilog or VHDL). Experience with FPGA development workflows (Quartus, Vivado, or similar). Familiarity with memory hierarchies, compute pipelines, and SoC architecture concepts. Proficiency in simulation and verification tools (ModelSim, Questa, or equivalent). Coursework or project experience in computer architecture or hardware acceleration. Exposure to high-performance computing or accelerator architectures. Knowledge of PCIe, DDR/HBM interfaces, and on-chip interconnects. Experience with scripting for automation (Python, TCL). Familiarity with Agilex or similar FPGA platforms.