Infineon

Compensation

Full Description

Coordinate with team members on the Design Entry, Development, and Implementation of custom AMS behavioral models and schematic netlisting for the purpose of performing high-quality pre-silicon verification of Engineering and Production ICs. Contribute, support and perform verification of DFT plans that may include support for digital scan chain testing. Contribute, support and perform verification of functionality performances, as well as ATE and Bench testability of Production ICs. Collaborate with various teams on the Design, Development and Verification of Engineering and Production ICs. BSEE/ME or equivalent with 3+ years' experience. Experienced with Cadence Virtuoso and Xcelium Tool Suite driven by the Hierarchy Configurations. Capable of creating schematics and generating netlist for simulation. Good understanding of analog design techniques. Understanding the signal flow and boundaries between the analog and digital domains. Extensive experience in the compiling, elaborating, and running of mixed-signal simulation in both ADE Explorer and Xcelium. Solid understanding of analog Spectre simulation and associated AMS modeling of analog circuit blocks. Solid debugging skills in both the analog and digital domains. Conversant in Verilog, Python, C, C++ and capable of generating simple scripts. Experience with Microsoft Office Tools (Word, Powerpoint, Excel) and Unix/Linux shell commands and editors. Experienced with version control systems. Experienced with bug reporting and tracking systems. Work well with teams but also a self-starter. We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.